In a semiconductor device including memory cells, a memory cell region provided with the memory cells is typically formed in the finest possible pattern (that is, having smallest possible feature sizes or spacing between features), and a peripheral circuit region provided in the periphery of the memory cell region is formed with feature sizes (or spacing between features) that is several to tens of times greater than that of the memory cells. Therefore, at the boundary between the memory cell region and the peripheral circuit region, the pattern density significantly changes. Therefore, during the patterning of the memory cell region, it becomes difficult to form the patterns at the center portion of the memory cell regions and at the region boundary at the same time with linearity.